Causes: • Wrong engine board installed. • Wrong controller board installed. • Check the type of engine board and controller board. • Replace BICU • Replace controller board
Remedy:
Code: 672
Description: Controller startup error. After power on, the line between the controller and the operation panel did not open for normal operation. -or- After normal startup, communication with the controller stopped.
Causes: An error was detected in the signal from the ASIC (controller board) which controls the STR (Suspend to RAM) function. Note: STR is a feature of this machine that minimizes energy consumption while the machine is in the energy saver mode.
Remedy: • Reboot the machine. • Replace the controller board.
Code: 819
Description: Fatal kernel error. Due to a control error, a RAM overflow occurred during system processing. One of the following messages was displayed on the operation panel. 0x5032 HAIC-P2 decompression error Error occurred in the compression/decompression module of ASIC Veena in HAIC-P2. If EFI (Fiery Controller) is connected, refer to the EFI manual. If EFI is not connected. • HDD defective • System memory defective 0x6261 HDD Defective There was no response from HDD. The power supply to the HDD may have been interrupted suddenly. • Re-format HDD. • Replace HDD 554C USB loader defect USB loader was detected as defective.
Causes: • System program defective • Controller board defective • Optional board defective • Replace controller firmware
Remedy: For more details about these SC code errors, execute SP5990 to print an SMC report so you can read the error code list. The error code is not displayed on the operation panel.
Causes: • System program defective • Controller board defective • Optional board defective • Replace controller firmware
Remedy: For more details about these SC code errors, execute SP5990 to print an SMC report so you can read the error code. The error code is not displayed on the operation panel.
Code: 821
Description: Self-diagnostic error: ASIC CTL The ASIC provides the central point for the control of bus arbitration for CPU access, for option bus and SDRAM access, for SDRAM refresh, and for management of the internal bus gate.